Apparatus for determining sticky bit value in arithmetic operations

ABSTRACT

An apparatus for determining the correct value to be assigned to the &#34;sticky-bit&#34; (S) position as a consequence of an arithmetic floating point multiply, divide or square root operation. The apparatus measures the number of trailing zeroes in the operand registers, performs a sum or difference calculation of these values, and compares the result with a third value to determine the sticky-bit value.

BACKGROUND OF THE INVENTION

The present invention relates to an apparatus for performing certainfloating point arithmetic operations in a data processing system. Moreparticularly, the invention relates to an apparatus simplifying thecompletion of floating point arithmetic operations by processing theoperands to form an early determination of the value of the "sticky bit"which appears in the floating point resultant value.

The use of floating point arithmetic operations in a data processingsystem has been a common practice practically since the inception ofcomputer technology. The development of floating point arithmetichardware has taken many forms, usually with the objectives ofsimplifying the hardware construction, or enhancing the speed of thearithmetic processing operation. The four arithmetic operations of add,subtract, multiply and divide have usually been accomplished by usingspecialized subsets of processes involving addition and subtraction. Forexample, multiplication operations have in many cases been performed byrepeated addition processes, and division has been accomplished by aprocess of repeated subtraction. The efforts made to speed up theseprocessing operations have focused on enhancements and simplificationsof hardware circuit design, particularly the adder circuit, whichultimately limits the maximum processing speed of all arithmeticoperations. In the case of division, efforts have been made to increasethe speed of operation by calculating partial quotients, or bysimultaneously predicting multiple quotient bits, to reduce the numberof addition or subtraction iterations required for the dividecalculation.

An American national standard has been developed in order to provide auniform system of rules for governing the implementation of floatingpoint arithmetic systems. This standard is identified as ANSI/IEEEStandard No. 754-1985, and is incorporated by reference herein. In thedesign of floating point arithmetic systems and algorithms, it is aprincipal objective to achieve results which are consistent with thisstandard, to enable users of such systems and algorithms to achieveconformity in the calculations and solutions to problems even though theproblems are solved using different computer systems. The standardspecifies basic and extended floating point number formats, arithmeticoperations, conversions between integer and floating point formats,conversions between different floating point formats, conversionsbetween basic format floating point numbers and decimal strings, and thehandling of certain floating point exceptions.

The typical floating point arithmetic operation may be accomplished ineither single precision or double precision format. Each of theseformats utilizes a sign, exponent and fraction field, where therespective fields occupy predefined portions of the floating pointnumber. In the case of a 32-bit single precision number the sign fieldis a single bit occupying the most significant bit position; theexponent field is an 8-bit quantity occupying the next-most significantbit positions; the fraction field occupies the least significant 23-bitpositions. In the case of a double precision floating point number thesign field is a single bit occupying the most significant bit position;the exponent field is an 11-bit field occupying the next-mostsignificant bit positions; the fraction field is a 52-bit fieldoccupying the least significant bit positions.

After each floating point answer is developed, it must be normalized andthen rounded. When the answer is normalized, the number of leading zerosin the fraction field is counted. This number is then subtracted fromthe exponent and the fraction is shifted left until a "1" resides in themost significant bit position of the fraction field.

In designing the hardware and logic for performing floating pointarithmetic operations in conformance with ANSI/IEEE Standard 754-1985,it is necessary and desirable to incorporate certain additionalindicator bits into the floating point hardware operations. Theseindicator bits are injected into the fraction field of the floatingpoint number, and are used by the arithmetic control logic to indicatewhen certain conditions exist in the floating point operation. Forexample, an "implicit" bit I is set to "1" by the arithmetic controllogic when the exponent of the floating point number has a nonzerovalue. The implicit bit I is created at the time a floating point numberis loaded into the arithmetic registers, and the implicit bit I occupiesthe first bit position in the fraction field of the number. In addition,a "guard" bit G is set by the floating point control logic duringcertain arithmetic operations, as an indicator of how to round. The Gbit occupies a position which is one bit less significant than the leastsignificant bit (LSB) of the result before rounding. Finally, a "sticky"bit S is an indicator bit which is set in all floating point arithmeticoperations when any bit of lower precision than the guard (G) bit is a"1," as an indicator that the floating point number has lost someprecision.

The extra bits in the fraction field are used exclusively for roundingoperations, after the result has been normalized. The guard (G) bit istreated as if it is a part of the fraction; it is shifted with the restof the fraction, and included in all arithmetic. The sticky (S) bit isnot shifted with the fraction, but is included in the arithmetic. Itacts as a "catcher" for 1's shifted off the right of the fraction; whena 1 is shifted off the right side of the fraction, the S bit will remaina 1 until normalization and rounding are finished.

In a rounding operation following the IEEE convention, there are fourmodes of rounding which are used, as follows:

1) round to nearest;

2) round to positive infinity;

3) round to negative infinity;

4) round to zero.

The "round to nearest" mode means that the value nearest to theinfinitely precise result should be delivered. If the two nearestrepresentable values are equally near, the one with its leastsignificant bit zero shall be delivered. The "round to positiveinfinity" mode means that the value closest to and not less than theinfinitely precise result should be delivered. The "round to negativeinfinity" mode means that the value closest to and not greater than theinfinitely precise result should be delivered. The "round to zero" modemeans that the result delivered should be the closest to but not greaterin magnitude than the infinitely precise result.

Unfortunately, any arithmetic circuit utilizing an adder for carryingout an addition or subtraction inevitably involves the generation ofcarry bits which are propagated from least significant bit positions tomore significant bit positions, and can in fact be propagated throughoutall bit positions during an arithmetic operation. This has the affect ofextending the processing time required for completing a calculation, andvarious design efforts have been made to deal with this problem. Forexample, U.S. Pat. No. 4,754,422, issued Jun. 28, 1988, discloses adividing apparatus utilizing three carry-save adders in an effort toproduce a plurality of quotient bits during each iteration or cycle ofarithmetic operation. U.S. Pat. No. 3,621,218, issued Nov. 16, 1971,discloses a high-speed divider utilizing a single carry-save adder forproducing a plurality of quotient bits during each iteration of thearithmetic operation, and a plurality of registers for holding asequence of partial quotients used in the operation.

U.S. Pat. No. 4,639,887, issued Jan. 27, 1987, discloses an apparatusfor decreasing the latency time associated with floating point additionand subtraction. The invention uses duplicate hardware for thecalculation of the arithmetic operation on the fraction portion of afloating point number, and then selects a resultant value based uponexponent differences.

In any floating point operation in a data processing system it isdesirable to increase the efficiency of one or more of the floatingpoint operations, for an increase in this efficiency translates directlyinto a proportionate time savings in systems operation. Certainefficiencies are possible in specialized situations, some of which areillustrated in the foregoing prior art disclosures, and it is importantto take advantage of these efficiencies, particularly if the specialsituations may be encountered relatively frequently during the course ofdata processing operations. For example, floating point arithmeticcalculations frequently require a normalize operation when an answer isdeveloped, and a rounding operation if the answer is inexact. However,either or both of these operations may be skipped when certain resultconditions exist, thereby saving the time otherwise required forexecuting these operations. In floating point multiply operations thenormalize and rounding steps can be eliminated approximately 50% of thetime, depending upon certain operating conditions, and for floatingpoint addition and subtraction operations the normalize and roundingsteps can be eliminated about 25% of the time, depending upon operatingconditions. By eliminating these steps when conditions suggest thatelimination is possible, an overall savings in computer processing timeis achieved.

The states of the guard (G), sticky (S), and the least significant bit(LSB), the resultant sign, and the rounding mode are all used todetermine whether or not the LSB should be incremented in order todeliver a correctly-rounded fraction result. The state of the sticky (S)bit must usually be known prior to delivering a final result.

SUMMARY OF THE INVENTION

The present invention provides a method and apparatus for processing theoperands to make a determination of the sticky (S) bit, independent ofthe floating point processing calculation, which may be ongoingsimultaneously with the processing according to the teachings of thepresent invention. The invention utilizes circuitry for detecting thenumber of trailing zeroes in each of the operands for which a floatingpoint operation is underway. The trailing zero detector logic for eachoperand is coupled into an adder to produce a sum value and a comparatorcompares this value against a predetermined value to determine the finalvalue of the sticky bit required for the arithmetic floating pointoperation. The invention may be used, with some variation, inconjunction with floating point multiply, divide and square rootcalculations.

It is the principal object and advantage of the present invention toprovide an apparatus for determining a resultant sticky bit valuesimultaneously while floating point computational processes are ongoing.

It is another object and advantage of the present invention to provide asticky bit value in floating point arithmetic operations, by processingthe operands utilized in the operations.

It is another object and advantage of the present invention to increasethe speed of overall floating point arithmetic operations.

The foregoing objects and advantages will become apparent from thefollowing specification, and with reference to the claims, and withreference to the drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of the apparatus for use in multiplicationoperations;

FIG. 2 shows a block diagram of the apparatus for use in divisionoperations; and

FIG. 3 shows a block diagram of the apparatus for use in square rootoperations.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention is useful for determining the proper sticky bit(S) value for both multiplication and division arithmetic operations.The invention may also be utilized for specialized division operations,such as square root arithmetic operations. The invention will bedescribed hereinafter, first with reference to a multiplicationoperation, and then with reference to a division operation, and finallywith reference to a square root operation. For all operations, theimplicit bit (1) is assumed to be a "1."

Multiply Operation

Referring to FIG. 1, an apparatus is illustrated for practice of theinvention in connection with a multiplication operation. The apparatusillustrated operates independently and simultaneously with the circuitryfor performing the actual multiplication calculation, and the apparatusproduces a sticky bit value which is available simultaneously with theresultant value determined from the multiplication circuitry.

The sticky bit value is calculated by determining the value of trailingzero bits in both the multiplicand and multiplier fraction operands. Thenumber of trailing zero bits in a fraction is a direction measure of theprecision of the operand; the precision of the input operands is used topredict the precision of the output fraction, as it would be representedif there were an unlimited number of bit positions. The predictedresultant fraction precision is used to determine the state of thesticky bit. To pre-determine the precision of a product result, it ishelpful to first consider the basic premises for multiplication of twobinary values. If L_(A) represents the length of a binary operand Awhich only encompasses the binary "1" values, all leading and trailingzeroes may be ignored along with the location of the binary point.Therefore, let L_(B) and L_(C) represent the length of operands B and C,in the same manner., If we examine the product C for the equation:

    A×B=C

The following relationship may be established:

    L.sub.A +L.sub.B -1≦L.sub.C ≦L.sub.A +L.sub.B

The following example illustrates the foregoing equations: ##STR1##

The apparatus illustrated in FIG. 1 performs the necessary comparisonsand calculations for determining the sticky bit value for the product ofany multiplicand fraction and any multiplier fraction. The exampleillustrates a double precision arithmetic operation, but a similarexample would apply to single precision, and single and double extendedprecision arithmetic operations, since the bit position location of thesticky bit is well known and established for all of these differentarithmetic operations.

The multiplicand fraction is held in a register 10, and the multiplierfraction is held in a register 20. Assuming a double precision design,the 52-bits of register 10 are monitored by a trailing zero detectorlogic circuit 12, which will produce a 6-bit binary output indicative ofthe number of trailing zeroes detected in circuit 12. Since any numberof trailing zeroes may exist, from 1-52, the 6-bit output binaryrepresentation is adequate to represent any number of trailing zeroeswhich may occur. The multiplier fraction held in register 20 issimilarly monitored by a trailing zero detector logic circuit 22.Circuit 22 produces a 6-bit binary output value which is indicative ofthe number of trailing zeroes detected in the multiplier fraction. Thebinary output values detected by circuits 12 and 22 are connected intoan adder circuit 30 which produces the sum of the two inputs at output31. The sum of two 6-bit input values may produce a 7-bit output value,and output 31 is capable of representing any 7-bit output value whichresults from the addition operation. Output 31 is coupled into acomparator circuit 40 which compares the output value to a constantnumerical value "51," which is connected as the second input intocomparator 40. The significance of the comparison relates to the size ofthe resultant fraction register, and the respective bit positions whichhave been selected to hold the guard bit (G) and the sticky bit (S). Itis well recognized that the multiplication of two 53-bit fractions(including the implicit bit) will produce a 106-bit fractional result ifabsolute precision is to be maintained. Since it is impractical todesign registers and storage locations of a size required for absoluteprecision, the various special purpose bits described herein have beeninvented, in order to contain the result in a fraction register size of53-bits, and at the same time retain a record of the relative precision,or lack of precision, which is produced in a multiply operation. Forthis reason, the three special purpose bit positions corresponding tothe implicit bit (I), the guard bit (G) and the sticky bit (S), havebeen devised to be carried along with their resultant, and to bedeveloped as a part of the overall multiplication operation. Thepurposes of these special bits have been hereinbefore described, whereinthe implicit (I) bit occupies bit position No. 1 relative to the overallfractional result. The actual resultant fraction occupies bit positions2-53, i.e., a 52-bit field. The guard bit (G) occupies bit position 54.Comparator 40 determines whether the sum of the two input precisions isless than or equal to the precision measured out to the guard bitposition. If the sum of the two input precisions is less than or equalto the precision measured out to the guard bit position, the sticky bitmust be equal to zero, which is the value which the multiplicationoperation will assign to the sticky bit, via a signal on line 41, so themultiplication process will force the sticky bit value to become setequal to zero. If the sum of the two input precisions is greater thanthe precision measured out to the guard bit position, the value of thesticky bit must be equal to "1," and a signal on line 42 at the outputof comparator 40 is used to force the sticky bit value to become equalto a "1."

There is the one case of indefiniteness which must also be considered;this case occurs if the sum of the two input precisions is equal to theprecision measured out to the sticky bit position. In this case, thevalue of the sticky bit is indefinite, since the precision lengthformula allows for two possible values of product precision, eithermeasured out to the guard bit position or to the sticky bit position.Therefore, in this case the sticky bit may not be predicted by thecircuit of FIG. 1, and the value of the sticky bit must be determined bythe process of multiplication of the fractions. However, in this casethere is no added delay, since there are no bits possible to the rightof the sticky bit position; the sticky bit value is therefore simplyequal to the value of the bit in the sticky bit position after apossible 1-bit normalization shift, and the circuit permits the stickybit position value to be determined by the multiplication operationitself, by a signal on line 43.

Divide Operations

One method for performing division of two binary numbers is to use aNewton-Raphson approximation for the reciprocal of the divisor which isthen multiplied by the dividend to form the quotient. Each iteration ofthe Newton-Raphson formula

    X.sub.i +1=X.sub.i *(2-D*X.sub.i),

where X_(i) is the current reciprocal and D is the divisor, produces anext reciprocal, X_(i) +1, which has twice as many bits of precision asthe previous reciprocal. If enough iterations are performed to obtain afinal reciprocal with a precision at least as great as that of the finalquotient desired, there will still be a possible error of 1-bit in itsleast significant position because of the way that the formula producesa reciprocal which may not be finitely representable when the quotientis. For example,

    1100/0011=0100;

however, the reciprocal of 0011 is 0.01010101010101 . . . , which ismultiplied by 1100 to produce 0011.11111111111 . . . , which will be1-bit in error in the least significant position wherever that positionis.

The technique described herein with respect to multiply operations mayalso be used in connection with divide operations. The example givenearlier, of using the operand lengths to determine the length of theproduct for multiplication, can be restated to apply to division todetermine the quotient length. A*B=C is the same as C/A=B. For divisionoperations, this leads to the equation

    L.sub.C -L.sub.A ≦L.sub.B ≦L.sub.C -L.sub.A +1

In division operations, an exact result will contain the difference inbit lengths (L_(C) -L_(A)), or the difference in bit lengths plus 1(L_(C) -L_(A) +1). Any other result length produces an inexact result.

Referring to FIG. 2, a block diagram of the logic circuits required forpredicting the sticky (S) bit for a divide operation is shown. Thedividend fraction is held in a register 100, and the divisor fraction isheld in a register 120. Register 100 and register 120 are each connectedto trailing zero logic detection circuits, register 100 being connectedto circuit 112, and register 120 being connected to circuit 122. Each ofthe trailing zero logic detection circuits produces a binary outputvalue which is indicative of the number of trailing zeros in therespective fractions. The output values from circuits 112 and 122 areconnected as inputs into a subtracter circuit 130, which is a two'scomplement adder, with a constant adjustment of +54; the output fromcircuit 122 is complemented. The output from subtracter circuit 130 isconnected as an input to comparator circuit 140.

After the division operation has been completed, the quotient fractionappears in register 150. Register 150 is connected to trailing zerologic detection circuit 152, which produces a binary output valueindicative of the number of trailing zeros in the quotient fractionmeasured from the guard bit position. The output from circuit 152 isconnected as an input to comparator circuit 140. Comparator circuit 140produces an output which is connected to the sticky bit (S) position inthe resultant register; i.e., if comparator 140 determines that the twoinput values are equal the output "S" on line 141 is zero, and ifcomparator 140 determines that the two input values are unequal theoutput "S" on line 141 is "1."

Square Root Operations

A square root arithmetic operation may be thought of as a special casedivide operation, wherein the dividend is known and a determination mustbe made to identify a divisor and quotient having equal values. In thiscase the "dividend" is referred to as the radicand fraction, and the"divisor" and "quotient" are referred to as "root fractions." Given aradicand fraction which is normalized, the significance of the radicandis the length of the fraction field minus the number of trailing zeros.The square root operation attempts to find a solution to the equation:

    Radicand (RAD)=Root*Root.

The technique described earlier may be used to determine the sticky bit(S) value for square root operations, with only minor modifications. Forexample, the equation for determining the significant bit lengthsreduces to the following:

    L.sub.ROOT =(L.sub.RAD +1)/2, or

    L.sub.ROOT =L.sub.RAD /2; whichever produces a whole integer.

Since the precision of the radicand is always less than or equal to themaximum fraction field length, the significance of the root can neverexceed 1/2 the fraction field length unless the root is irrational andhas infinite length (for example, the square root of 2). Therefore, forall cases where the root significance is not infinite, the sticky bit(S) will be zero and the number of bits of significance L_(ROOT) isdetermined as shown above. The problem then becomes one of determiningwhen the root will have infinite significance, and thus have a stickybit (S) of "1."

FIG. 3 shows a block diagram for determining the sticky bit (S) value insquare root operations. The radicand is held in register 200, andregister 200 is connected to a trailing zero logic detection circuit212. Circuit 212 is connected to a "divide by 2" circuit 230, which maymerely be a circuit for right shifting the output value by one position,prior to connecting the output value to an input of comparator 240. Theother input to comparator 240 is connected to the output from trailingzero logic detector circuit 252. Circuit 252 receives its input from theresultant root fraction register 250. If comparator 240 determines thatthe number of trailing zeros from circuit 230 are equal to the number oftrailing zeros from circuit 252, the signal on output line 241 forcesthe sticky bit (S) position to a zero; if comparator 240 determines thatthe number of trailing zeros from circuit 230 are not equal to thenumber of trailing zeros from circuit 252, the signal on output line 241forces the sticky bit (S) position to a "1."

The present invention may be embodied in other specific forms withoutdeparting from the spirit or essential attributes thereof, and it istherefore desired that the present embodiment be considered in allrespects as illustrative and not restrictive, reference being made tothe appended claims rather than to the foregoing description to indicatethe scope of the invention.

What is claimed is:
 1. An apparatus for determining the sticky bit valueas the result of a floating point divide operation in a binary computerprocessor, comprising:a) a first register means for holding the dividendfraction, and a second register means for holding the divisor fraction;b) a first and second trailing zero detector circuit respectivelyconnected to each of said first and second register means, includingmeans for providing an output representing the number of trailing zeroesin said register means; c) a subtractor circuit connected to saidtrailing zero detector circuits said subtracter circuit having an outputrepresentative of the difference between the number of trailing zeroesin said respective register means; d) a comparator circuit having afirst input connected to receive said subtractor circuit output, andhaving a second input; e) a quotient fraction register means for storingthe quotient resulting from a division calculation of said dividendfraction and said divisor fraction; f) a third trailing zero detectorcircuit connected to said quotient fraction register, including meansfor providing an output representing the number of quotient fractiontrailing zeroes; said output being connected to the second input of saidcomparator, said comparator having an output for producing a sticky bit"1" value when said first and second inputs are unequal and a sticky bit"0" value when said first and second inputs are equal.
 2. The apparatusof claim 1, wherein said subtracter circuit further comprises an outputrepresentative of the difference between the number of trailing zeroesin said respective register means, modified by a constant value.
 3. Theapparatus of claim 1, wherein said comparator further comprises meansfor generating a first output signal when said number of trailing zeroesin said quotient register is equal to the difference of the number oftrailing zeroes in said first and second register means, and means forgenerating a second output signal when said number of trailing zeroes insaid quotient register is unequal to the difference of the number oftrailing zeroes in said first and second register means.
 4. Theapparatus of claim 1, wherein the first and second register meansfurther comprises a single operand register.
 5. The apparatus of claim4, wherein the subtracter circuit further comprises a divide-by-twocircuit having means for right-shifting the trailing zero detectioncircuit output one bit position.
 6. The apparatus of claim 5, furthercomprising a root fraction register having means for storing the squareroot value of the operand value stored in the operand register.
 7. Theapparatus of claim 6, further comprising a trailing zero detectorcircuit connected to said root fraction register, including means forproviding an output comprising the number of trailing zeroes in saidroot fraction register.
 8. The apparatus of claim 7, wherein saidcomparator further comprises an input connection to receive the numberof trailing zeroes in said root fraction register, and further comprisesmeans for generating a first output signal when said number of trailingzeroes in said root fraction register is equal to the right-shiftedoutput from the divide-by-two circuit.
 9. The apparatus of claim 8,wherein said comparator further comprises means for generating a secondoutput signal when said number of trailing zeroes in said root fractionregister is unequal to the right-shifted output from the divide-by-twocircuit.